An Adaptive Parallel Genetic Algorithm for VLSI-Layout Optimization
نویسندگان
چکیده
The generation of a high quality layout during the design of a VLSI microchip is a very complex combinatorial optimization prob lem Components of a circuit have to be placed and signal nets have to be routed on an overall minimal area In this paper a parallel Genetic Algorithm for the combined optimization of placement and routing is presented The main focus is on the self adaptation of the search pro cess Several islands execute a sequential GA with di erent strategies At xed intervals these strategies are ranked and each strategy is adjusted to the next better one by assimilating its characteristical parameters
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تاریخ انتشار 1996